#ifndef STM32F1_PWR_H_
#define STM32F1_PWR_H_

#include <stdint.h>
#include "iodef.h"

typedef struct {
        __IO uint32_t CR;
        __IO uint32_t CSR;
}pwr_reg_t;

#define PWR_CR_LPDS             _BIT(0)
#define PWR_CR_PDDS             _BIT(1)
#define PWR_CR_CWUF             _BIT(2)
#define PWR_CR_CSBF             _BIT(3)
#define PWR_CR_PVDE             _BIT(4)
#define PWR_CR_PLS_MASK         _VALUE(5, 0x7)
#define PWR_CR_PLS_2(n)         _VALUE(5, (n - 2))
#define PWR_CR_DBP              _BIT(8)  /* 1: Access to RTC and Backup registers enabled */

#define PWR_CSR_WUF             _BIT(0)
#define PWR_CSR_SBF             _BIT(1)
#define PWR_CSR_PVDO            _BIT(2)
#define PWR_CSR_EWUP            _BIT(8)

#define pwr     ((pwr_reg_t *)PWR_BASE)

#endif /* STM32F1_PWR_H_ */
